JPH0563829B2 - - Google Patents

Info

Publication number
JPH0563829B2
JPH0563829B2 JP59091221A JP9122184A JPH0563829B2 JP H0563829 B2 JPH0563829 B2 JP H0563829B2 JP 59091221 A JP59091221 A JP 59091221A JP 9122184 A JP9122184 A JP 9122184A JP H0563829 B2 JPH0563829 B2 JP H0563829B2
Authority
JP
Japan
Prior art keywords
data
data transfer
address
control device
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59091221A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60235269A (ja
Inventor
Masayuki Hanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59091221A priority Critical patent/JPS60235269A/ja
Priority to US06/731,941 priority patent/US4723223A/en
Publication of JPS60235269A publication Critical patent/JPS60235269A/ja
Publication of JPH0563829B2 publication Critical patent/JPH0563829B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59091221A 1984-05-08 1984-05-08 デ−タ転送制御装置 Granted JPS60235269A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59091221A JPS60235269A (ja) 1984-05-08 1984-05-08 デ−タ転送制御装置
US06/731,941 US4723223A (en) 1984-05-08 1985-05-08 Direct memory access controller for reducing access time to transfer information from a disk

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59091221A JPS60235269A (ja) 1984-05-08 1984-05-08 デ−タ転送制御装置

Publications (2)

Publication Number Publication Date
JPS60235269A JPS60235269A (ja) 1985-11-21
JPH0563829B2 true JPH0563829B2 (en]) 1993-09-13

Family

ID=14020366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59091221A Granted JPS60235269A (ja) 1984-05-08 1984-05-08 デ−タ転送制御装置

Country Status (2)

Country Link
US (1) US4723223A (en])
JP (1) JPS60235269A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7567779B2 (en) 1993-07-30 2009-07-28 International Multi-Media Corporation Sub-orbital, high altitude communications system

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CA1242809A (en) * 1985-12-20 1988-10-04 Mitel Corporation Data storage system
JPS6356754A (ja) * 1986-08-28 1988-03-11 Toshiba Corp 入出力チヤネル
US5134699A (en) * 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
US5121480A (en) * 1988-07-18 1992-06-09 Western Digital Corporation Data recording system buffer management and multiple host interface control
JP2637788B2 (ja) * 1988-09-02 1997-08-06 株式会社日立製作所 ディスクキャッシュ制御方式および情報処理システム
JP2836081B2 (ja) * 1989-01-12 1998-12-14 日本電気株式会社 ディスク制御回路
US5341479A (en) * 1989-01-31 1994-08-23 Storage Technology Corporation Address mark triggered read/write head buffer
US5475631A (en) * 1989-03-09 1995-12-12 Micron Technology, Inc. Multiport RAM based multiprocessor
JPH02299052A (ja) * 1989-05-12 1990-12-11 Victor Co Of Japan Ltd Ｄｍａコントローラ
US5287471A (en) * 1989-07-24 1994-02-15 Nec Corporation Data transfer controller using direct memory access method
JP2907451B2 (ja) * 1989-08-31 1999-06-21 キヤノン株式会社 ダイレクトメモリアクセス方法および装置
DE69031983T2 (de) * 1989-10-10 1998-07-30 Storage Technology Corp Mehrschritt-datenlesevorrichtung
JP3055917B2 (ja) * 1990-05-22 2000-06-26 日本電気株式会社 データ転送制御装置
JPH0496163A (ja) * 1990-08-08 1992-03-27 Nec Corp Ｄｍａコントローラ
WO1993003438A1 (en) * 1991-08-07 1993-02-18 Adaptec, Incorporated Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive
DE4127579A1 (de) * 1991-08-21 1993-02-25 Standard Elektrik Lorenz Ag Speichereinheit mit einem adressgenerator
JP3451099B2 (ja) * 1991-12-06 2003-09-29 株式会社日立製作所 外部記憶サブシステム
CA2131627A1 (en) * 1992-03-09 1993-09-16 Yu-Ping Cheng High-performance non-volatile ram protected write cache accelerator system
US5754889A (en) * 1993-12-22 1998-05-19 Adaptec, Inc. Auto write counter for controlling a multi-sector write operation in a disk drive controller
US5742789A (en) * 1995-12-28 1998-04-21 Emc Corporation Dynamically adaptive data retrieval for a disk drive storage system
US5805787A (en) * 1995-12-29 1998-09-08 Emc Corporation Disk based disk cache interfacing system and method
US6065100A (en) * 1996-11-12 2000-05-16 Micro-Design International Caching apparatus and method for enhancing retrieval of data from an optical storage device
US5946708A (en) * 1997-01-24 1999-08-31 Integrated Memory Logic, Inc Automated cache manager for storage devices
US6055583A (en) * 1997-03-27 2000-04-25 Mitsubishi Semiconductor America, Inc. DMA controller with semaphore communication protocol
US5991847A (en) * 1997-06-06 1999-11-23 Acceleration Software International Corporation Data pattern caching for speeding up write operations
US6332176B1 (en) 1998-08-07 2001-12-18 Integrated Memory Logic, Inc. Autohost controller
US6574682B1 (en) * 1999-11-23 2003-06-03 Zilog, Inc. Data flow enhancement for processor architectures with cache
US7219169B2 (en) * 2002-09-30 2007-05-15 Sun Microsystems, Inc. Composite DMA disk controller for efficient hardware-assisted data transfer operations
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
US8661169B2 (en) * 2010-09-15 2014-02-25 Lsi Corporation Copying data to a cache using direct memory access

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756420A (fr) * 1969-11-10 1971-03-01 Ibm Dispositif de transfert d'enregistrements
US3829837A (en) * 1971-06-24 1974-08-13 Honeywell Inf Systems Controller for rotational storage device having linked information organization
JPS5255446A (en) * 1975-10-31 1977-05-06 Toshiba Corp Information transfer control system
US4232365A (en) * 1978-03-01 1980-11-04 Sperry Corporation Apparatus for determining the next address of a requested block in interlaced rotating memories
US4399503A (en) * 1978-06-30 1983-08-16 Bunker Ramo Corporation Dynamic disk buffer control unit
US4300193A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having data multiplex control apparatus
US4535420A (en) * 1979-09-26 1985-08-13 Sperry Corporation Circular-queue structure
US4403283A (en) * 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
US4425615A (en) * 1980-11-14 1984-01-10 Sperry Corporation Hierarchical memory system having cache/disk subsystem with command queues for plural disks
US4400772A (en) * 1980-12-30 1983-08-23 International Memories, Inc. Method and apparatus for direct memory access in a data processing system
US4490782A (en) * 1981-06-05 1984-12-25 International Business Machines Corporation I/O Storage controller cache system with prefetch determined by requested record's position within data block
US4509118A (en) * 1982-05-25 1985-04-02 Honeywell Information Systems Inc. Method and apparatus for defining magnetic disk track field lengths using a programmable counter
US4543626A (en) * 1982-12-06 1985-09-24 Digital Equipment Corporation Apparatus and method for controlling digital data processing system employing multiple processors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7567779B2 (en) 1993-07-30 2009-07-28 International Multi-Media Corporation Sub-orbital, high altitude communications system

Also Published As

Publication number Publication date
JPS60235269A (ja) 1985-11-21
US4723223A (en) 1988-02-02

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